Hi everyone,

I’m currently working as an FPGA Engineer and will complete 1 year in a couple of months. Before joining my current company, I also had experience as a VLSI intern.

My actual work differs somewhat from my job description. I’ve mainly worked in server and data center environments, focusing on hardware validation, system-level debugging, platform bring-up, component testing, and software/scripting tasks.

I’m now trying to decide which direction to take for my next role. I’m more interested in FPGA/VLSI, but my current experience is mainly on the server validation/hardware side.

My questions:

1. What roles should I realistically target with my current background? Should I focus on VLSI/FPGA, which I enjoy, or continue down the validation/hardware/firmware path, which reflects my current experience?
2. Is it a good idea to switch after only ~1 year of experience? My concern is that if I stay here, I’m unlikely to get much FPGA work, even though that was the direction I originally intended to pursue.
3. If I decide to switch to FPGA/VLSI, how should I position my current experience on my resume? How much value does server validation/hardware debugging experience have for FPGA/RTL roles?
4. For someone with ~1 year of experience trying to make this transition, what should I learn well enough to actually make a difference in interviews?

Would really appreciate advice from people working in FPGA, RTL/VLSI, server hardware, validation, or firmware.

I’m trying to choose a direction now rather than spend another couple of years accidentally becoming an expert in everything except the thing I actually wanted to do. 😭

Hi guys, thought i’d show you this cool animation of how the MAC Array in my Neural Network Accelerator performs matrix-vector computations during inference for a model on topology 4:3:2 neurons per layer.

The values for the parameters (weights and biases ) and input features were randomly selected just for demonstration purposes.

Let me know what you guys think:).

Github repo: https://github.com/Shingyy/MAC-Array-based-DNN-Accelerator

When x is high, y shd be high for 80 to 100 cycles. Write a assertion for this.

I gave this answer

assert property( @(posedge clk) x |=> y[*80:100]);

The interviewer said its wrong and gave me some simulations for example. In the end I didn’t get the answer and the only thing he said was the answer is shorter than the one I gave. Can anyone try to solve this?

Sim 1:
0,x = 1
1-125,x=0
0,y = 0
1-80,y=1
81-100,y=0/1
101-125,y=0

Sim 2:
0-200,x=1
201-500,x=0
0,y=0
1-280,y=1
281-300,y=0/1
301-500,y=0

Sim 3:
0,x=1
1-19,x=0
20,x=1
21-39,x=0
40,x=1
41-500,x=0
0,y=0
1-120,y=1
121-140,y=0/1
141-500,y=0

I am wanting to create an enclosure for the AUP-ZU3. I'm wondering if anyone has mech drawings to save myself some time.

Thanks!

TL,DR: I am new to FPGAs, a simple .vhd core cannot run at high frequencies, I have no idea if it is me or the chip I am using. Does "my" timing comparison analysis make any sense? Does the CCGM1Ax under-perform so bad?

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I am new to FPGAs. I have been learning VHDL for the past 2 months because I got pissed off at how unpredictable MCUs can be. As a first FPGA, I got myself the Cologne Chip's evaluation board (CCGM1A1-E1) to be implemented in my hardware project. It is not exactly a widely adopted FPGA, so real cases and reviews are hard to find.

In my project, I need to drive an H-bridge using some fucky modulation techniques. And, as for any power electronics, dead-time is needed. Originally I had the dead-time implemented in the modulation core, but since I am using GaN FETs, I tried to implement very small dead-times (10ns is the goal). This would require a very high fabric clock, to the point that the modulation itself was not feasible anymore, so I decided to create a dedicated dead-time core running at high frequencies and keep the modulation core at a modest frequency.

(for those who are not familiar with dead-time in a half-bridge configuration, just think as "delay a rising edge by a very small time" logic)

For this dead-time core, I kept the logic as simple as I could and cranked the frequency to it. Since I am a beginner and my dead-time core likely sucks, I need at least 2 dead-time clock cycles to perform the logic for the rising edge detection section: I was aiming for a frequency of 196.608MHz, or a period of ~5.09ns. So two of these periods would result in about the 10ns I want. If it performed really well, I would go for 393.216MHz.

After doing the place and route shenanigans, it came back with a constraint of 192.6MHz maximum (goal of 196.608MHz). Since it missed by just a hair, I tried a few more times to see if the PNR could arrange things better. Spoiler alert: it didn't.

Two days banging my head on the wall later, hoping an answer would leak from my cracked skull, I gave up and asked my "AI tutor".

(note: since I want to *really* learn VHDL, my "AI tutor" is an agentic model using a competent LLM (DeepSeek v4 in this case) that is instructed to *never* give me full answers or large sections of code, or alter my .vhd codes for me, only to "give the user the bare minimum to aid them to go back in the right track, preferably forcing the user to think by themselves to find the solution with hints", "no matter if it is to implement something new or fix something existing").

My matrix-y tutor came back with a conclusion that running my dead-time core at 196.608MHz is simply impossible. I asked it estimate the maximum frequency in other chips from the "big 3 manufacturers" using well-documented online findings:

Your DT critical path is just one LUT deep — you can't make the logic any shallower. The fact that even that only reaches ~193 MHz on the GateMate tells you the raw fabric capability of this device is around 190–200 MHz for any FF-to-FF path. That puts the GateMate at the very low end of the market. Approximate FF-to-FF fabric ceilings (order of magnitude, not exact):

Device (process) Simple-path fabric fmax

Cologne Chip GateMate (28 nm) ~190–200 MHz (measured, yours)

Lattice iCE40 (40 nm) ~150–300 MHz

Lattice ECP5 (40 nm) ~250–400 MHz

Intel Cyclone V (28 nm) ~300–450 MHz

Xilinx Spartan-7 / Artix-7 (28 nm) ~400–550 MHz

Xilinx Kintex/Virtex UltraScale+ (16 nm) ~500–700 MHz

Intel Agilex / Stratix 10 (10/14 nm) ~500–800 MHz

This... surprised me. And not in a good way.

Since I am new to FPGAs, and LLMs are not All-Knowing Gods (even though vast majority of the population treats these "next-word-prediction statistics model" as such), I would like to ask the Council of The Wise Ones (a.k.a. strangers in r/FPGA): does this make any sense? Or did the LLM made some mistake and over-estimated all other FPGAs?

Is it true that the CCGM1Ax FPGA under-perform its competitors by quite a large margin?

Thank you for going through this massive wall of text!

PS: these "weird" frequency values used are due to the external clock generator running at 24.576MHz (because audio applications), so all other frequencies in my project are either integer multiples or integer dividers of it.

Is it possible?

Vivado GUI-based Project Mode is convenient for initial setup and development.
However, as a project grows and more developers begin collaborating, source files, generated files, and project-specific settings can become increasingly difficult to manage and maintain under version control.

To address these challenges, this development environment was built around Vivado Tcl-based Non-Project Mode, where the entire workflow—including build, simulation, bitstream generation, and FPGA programming—is managed through scripts.

I coded a SoC that includes a multi-cycle risc-v core, some peripherals and an acceleretor. And then, I also completed its FPGA implementation. On FPGA i achieved ~50 MHz clock frequency. But, when I try to complete the SoCs asic design flow on LibreLane with sky130 pdk i only achieve ~25 MHz clock frequency. As I know, VLSI implemented design should be able to work with higher clk freqs than FPGA. Why is that happening? Is that because of LibreLane or sky130?

edit: the fpga i implemented my project is basys3

Xilinx 7-series, Vivado, Clocking Wizard 6.0. Board clock is 40 MHz. I need a

921600 baud UART.

The ratio is awkward: 40e6 / 921600 = 3125/72. That 5^5 in the denominator means

there is no all-integer (M, D, O) solution — I brute-forced every legal

combination and the only way to land on an exact multiple of 921600 is with the

MMCM's fractional CLKOUT0 divide. A PLL can't do it at all (integer only).

What I ended up with:

Option A: M=27, D=1, VCO=1080 MHz, CLKOUT0=9.375 -> 115.2 MHz

counter /125, 1-clock-wide enable pulse

Wizard reports 164.6 ps pk-pk jitter

Option B: M=18, D=1, VCO=720 MHz, CLKOUT0=3.125 -> 230.4 MHz

counter /250 with a toggle FF, gives a 50% duty square wave

Wizard reports 187.4 ps pk-pk jitter

Both give exactly 921600 Hz with zero frequency error, which is nice. But the

jitter numbers feel high to me compared to the ~100 ps I usually see from an

all-integer MMCM config, and I assume the fractional divider is the cause.

Questions:

1. For a UART is ~180 ps pk-pk on the source clock just a non-issue? My napkinmath says it's 0.017% of a 1085 ns bit period and the frequency error iszero so nothing accumulates across a frame — but I'd like a sanity checkfrom someone who has actually shipped this.
2. Is there a reason to prefer a fractional accumulator (acc += 72, threshold3125, tick on overflow) running straight off the 40 MHz clock instead? Thatneeds no MMCM at all, gives an exact average baud rate, and trades clockjitter for +/-25 ns of deterministic quantisation on each bit edge. Feelscleaner but I've mostly seen the "MMCM to a magic frequency, then divide"pattern in other people's code.
3. Option B needs the counter to run at 230.4 MHz just to get a 50% duty cycleI don't actually need (it's an internal clock enable, never leaves the chip).Am I right that Option A is strictly better here?
4. Anything else I should be worried about with fractional CLKOUT0 divides thatthe Wizard's summary page doesn't tell me?

Part is xc7k325tffg676-1

I can't lie, I forget a lot of C++ since that was like 2 years ago and I haven't paid much attention since. How many problems are there for the C++ section usually and how bad are they really from the perspective of someone who knows like bare minimum C++ syntax and then knows some RTL stuff? Need help ASAP thx

Hey I’m trying to pitch an idea to a software lead at a club I’m trying to join at my university. It’s their URC Rover team.

They currently use a Jetson and RTOS for all the embedded work regarding computer vision. I’m really into FPGAs so I was thinking of trying to incorporate it where the FPGA and Jetson work together.

Has anyone done something similar? Any advice from those who have?

I’m an engineering student planning my senior design project and would like some feedback.
I’m considering a RISC-V controlled runtime-configurable INT8 MAC accelerator on a PYNQ-Z2, using VexRiscv and MobileNetV2.
The idea is to have different MAC modes:
4×4 → 16 MACs
8×8 → 64 MACs
16×16 → 256 MACs
The RISC-V CPU would select the MAC configuration at runtime based on the workload. I’d compare fixed vs adaptive configurations based on latency, power, energy, resource usage, and MAC utilization.
I was inspired by a recent paper on runtime-reconfigurable RISC-V accelerators with software fallback and FPGA DPR.
Do you think this is a good/realistic senior design project? Is there enough novelty, and what would you change or add?

Folks who are in HFT FPGA team for more than 1-2 years, what are the resources you still follow

I am a digital design engineer with about 10 years of experience and I’ve spent the past several months building Booley, an open-source development environment for using LLM coding agents on RTL projects (for FPGAs and ASICs both)

The basic idea is that an agent should be treated as a talented junior engineer - can write decent RTL and testbenches, but inexperienced with EDA tools, often does stupid design decisions and can potentially force push and break your git history. In Booley, agents run inside an isolated container and receive structured access to the sim, synth and lint workflows (mostly open-source tools right now, but also supports Vivado). It can also inspect simulator traces through a CLI rather than trying to reason about sequential behavior from the RTL alone.

Booley grew out of problems I repeatedly encountered while using raw Claude/Codex:

• They often skipped EDA tool checks unless explicitly prompted.
• They selected the wrong configuration or misunderstood tool reports
• They tried to debug complex sequential logic without examining waveforms.
• Their generated testbenches concentrated on happy paths.
• Giving them enough permissions to work independently put the dev machine at risk

Booley does not attempt to replace architectural judgment or make generated RTL trustworthy by itself. The engineer still owns the specification, design decisions and final review. The goal is to make agents better at executing bounded RTL tasks and completing the verification loop, while also making the review process more convenient for humans.

Right now for FPGA designs specifically Booley offers design of platform-independent RTL and out-of-context implementation in Vivado to get resource and frequency estimations. Mapping pins, generating clocks using PLL and other very FPGA-specific steps for your design you will still have to do in Vivado

I’d particularly appreciate criticism from people working in RTL design or verification:

• Do you experience the same kinds of issues when working with raw Claude/Codex or am I trying to solve issues that don’t really exist?
• Where would this approach break down in a real project?
• What FPGA-specific features is Booley missing?

The project, videos demonstrating it in action and quick start Demo are here:

https://github.com/boldaxolotl/booley

Booley source code is designed by me and is written by LLM agents

I’m the author and happy to answer technical questions

Hello everyone. I'm considering to buy PYNQ Z2 board and saw that some boards named as TUL PYNQ Z2 and DFRobot PYNQ Z2. These DFRobot ones are sold on Mouser Digikey for ~260$ and TUL named ones are sold on Aliexpress for ~190$. Which site or version should I choose?

Hi everyone. I previously posted here after accidentally shorting the 3.3 V rail to GND on a Terasic DE0-Nano:

https://www.reddit.com/r/FPGA/comments/1v8b80t/accidentally_shorted_33v_to_gnd_on_de0nano/

The board belongs to my university, and I now need to replace it with the exact same model: the Terasic DE0-Nano P0082 with the Altera Cyclone® IV EP4CE22F17C6N FPGA.

I live outside the United States, but I have a family member in Florida who can receive the package and bring it to me on an upcoming trip. Therefore, I would have DigiKey ship it to their residential address in the US rather than ship it internationally.

I found this DigiKey listing for about $120:

https://www.digikey.com/en/products/detail/terasic-inc/P0082/2625112

DigiKey lists the contents as “Board(s), Cable(s),” but the packaging type says “Bulk.” I want to confirm that this means the fully assembled and genuine DE0-Nano board with its USB programming cable, rather than a bare board or incomplete product.

The same board is available on Amazon for around $220, but paying an extra $100 seems unnecessary if DigiKey is a reliable authorized distributor.

Has anyone purchased this exact P0082 listing from DigiKey? Did it include the fully assembled board and USB Mini-B cable? Is there any issue with ordering from outside the US while having it delivered to a family member’s US residential address?

Would you consider DigiKey the safer option compared with an Amazon marketplace listing?

Thanks again for all the help.

I'm a 3rd-year CS student specializing in Computer Architecture. Last semester I had to simulate VHDL designs and the experience was painful: Heavy GUIs, half an hour of setup just to see a waveform (specially on windows, where we work)

So I spent the summer building my own: a VHDL simulation engine in C++20 with a full compilation pipeline and a terminal UI debugger for waveform inspection. TUIs are having a moment right now and I think hardware tools deserves one too.

It's open source. Repo: https://github.com/oscar30gt/pulse — feedback and ⭐ is really appreciated.